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NXP/ST Power Architecture / MPC560x, SPC560P, SPC560B: Watches & Disassembly showing illegal instructions 13-Mar-2025
Later in the debug session, after observing a certain variable through a pointer or directly, some or all the values in the Watch windows get corrupted and the Disassembly Window displays the message Illegal Instructions . The value of the variable is not modified, it is only read. Possibl...
NXP/ST Power Architecture: Trace trigger doesn't work – Analyzer remains in WAITING state 13-Mar-2025
Nexus Event Out Pin (EVTO) signal is used in winIDEA as a trace trigger, but it is not enabled. Possible solution To generate the trigger event (EVTO), enable it in the Trigger Configuration dialog. 1. Open View | Analyzer . 2. Click the Analyzer Configuration button. 3. Check the Manual H...
Infineon AURIX: HSM breakpoints not recognized after application reset 13-Mar-2025
This topic explains what an application reset is, why it affects breakpoint detection, and provides potential workarounds for debugging HSM (Hardware Security Module) cores effectively. What is an application (software) reset? In the context of AURIX debugging, an application reset refers ...
Infineon AURIX: How to release Watchdog from the suspend mode? 13-Mar-2025
When AURIX devices are in debug mode, Watchdog is enabled by default , but the Watchdog Timer is unconditionally suspended (stopped), which means that the Watchdog never resets the chip. To use the Watchdog during debugging, you have to disable the Watchdog Timer suspended logic (or enable...
Renesas RH850: Challenge & Response Authentication 13-Mar-2025
This topic describes how to enable PE and ICUM debugging using Python scripts when the Challenge & Response Authentication is enabled. Intelligent Cryptographic Unit Master (ICUM) is a RH850 HSM core that can run secure cryptographic operations. The ICUM is disabled at the device shipment....
Synchronizing multiple cores 13-Mar-2025
Multiple cores are hardware-wise not synchronized by default after reset. Possible solutions Enabling multi-core synchronization 1. Enable the option S ynchronize selected cores (stop/run) when possible in Hardware |CPU Options |Debugging. 2. Enable synchronization in Hardware |CPU Options...
Hardware is not working or malfunctions 13-Mar-2025
Delivering deeply tested products is our quality objective, nevertheless, all BlueBox systems come with a warranty. TASKING provides a free exchange system or a free repair during the warranty period if the hardware malfunction is not the result of an overvoltage, mechanical damage, or dam...
Infineon AURIX TC2xx/TC3xx: From INI files to winIDEA GUI settings - synchronization & peripheral suspension configuration guide 13-Mar-2025
This guide helps with the transition from using the INI files to using winIDEA GUI settings to configure synchronization and peripheral suspension. If you are also migrating from an old winIDEA version, please refer to the general transition guide as well. In the older winIDEA versions ( 9...
Infineon AURIX TC2xx / TC3xx: HSM application is not running / HSM core is stopped 13-Mar-2025
When the AURIX is reset with the debugger connected and the Hardware Security Module (HSM) is enabled in the User Configuration Block (UCB), the boot code of TC2xx / TC3xx sets a breakpoint to HSM’s first instruction. This stops the HSM core from running and if the primary core expects the...
Arm VX-toolset: Integrating NXP S32 Design Studio 10-Mar-2025
S32 Design Studio (S32DS) is one of the IDEs we support, allowing you to integrate winIDEA’s debugging capabilities into your development workflow. Solution 1. Install VX-toolset for Arm v7.1r1 S32 v3.6.0. Older versions of S32 Design Studio are not compatible. 2. Start S32DS. 3. Select He...