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There are various ways to boot the NXP S32R294 in non-secure mode depending on the development stage of your project. The how-to guide below provides solutions for different examples. Solution Refer to NXP S32R294: Non-secure boot in winIDEA Help. More resources in winIDEA Help How to prog...
For SoCs (e.g. AM24xx, AM64xx, AM26xx) with multiple cores organized into clusters, you must manually select the memory area (bus) to successfully perform Debug | Download . Possible solution Specify Memory area (bus) 1. Open Debug |Configure Session |SoCs |Program Files |Program File . 2...
JTAG Chain scan functionality enables you to define IR/DR Prefix/Postfix values which could be entered in Hardware |CPU Options |JTAG . That is important when several devices are connected in a chain and you want to debug for example the second one. Possible solution From winIDEA build 9.2...
Possible causes Emulation start failed Instable connection Download not working UMI errors Write to Memory Window fails or memory read fails Solution Upgrade ST-Link firmware using ST firmware upgrade tool.
When debugging a Texas Instruments AWR family device, it is possible that the RAM download after a reset/power cycle fails. Possible solution A soft reset is needed. Use the SoftResetCR4 script . More resources Arm Cortex architecture-specific notes -winIDEA Help
Cypress Traveo II packages (64-pin, 80-pin, 100-pin, and 144-pin) have different trace capabilities. The following Emulation Adapters provide the trace interfaces, where a trace port is not available or lacks the full trace capability: CYT2B9 CYT2B7 CYT2BL By default, port pins P18 (P18_3 ...
When the CPU executes a (watchdog) reset, it triggers a CORERESET exception. By default, the debugger is set to catch such an exception and halts the CPU, which is indicated by the STOP-VCATCH Debug status. Possible solution 1. Open Hardware | CPU Options | Cores . 2. Make sure CORERESET i...
System reset or download (Error 258) fails on XMC1000 and NXP LPC family devices, when the debugger uses the reset vector catch mechanism to stop the CPU after the CPU reset release. Possible solution Always leave the CORERESET exception unchecked. 1. Open Hardware | CPU Options | CORE0 . ...
After issuing a Resetin winIDEA, the primary core (Cortex-M0+) is stopped at the reset vector, while the secondary core(s) are IDLE (Debug status IDLE will be shown). The secondary core(s) are then started by the application running on the primary core. Configuring Hardware |CPU Options |C...
To download and run an application in DDR RAM on AMD Zynq UltraScale+ using winIDEA, refer to Initialize AMD Zynq UltraScale+ DDR RAM how-to guide. More resources Add a custom initialization script
winIDEA enables an alternate debug session initialization if issues with downloading occur. This only affects download operations. Possible solution 1. Add the custom initialization script to Hardware | CPU Options | Reset | Initialization before programming | Connect . 2. Select Yes in th...
The debugger programs the code directly into the internal Flash memory through the standard Debug Download and based on the selected CPU: Identifies which code from the download file fits into the internal Flash. Loads it to the Flashthrough the flash programming procedure. The Flash progr...
Specific settings should be configured for this device so the trace trigger works correctly. Possible solution 1. Open Hardware | CPU Options | CTM/CTI . 2. Check in CTM Channel 2: R5.0˜ETMTRIGGER in TRIGINs. TPIUTRIGIN in TRIGOUTs . More resources in winIDEA Help CTM/CTI
For WLCSP packages, the boot loader changes the default pin configuration to: PIO0_2 register - SWCLK PIO0_3 register - SWDIO TCK_PIO0_5 register - PIO0_5 SWDIO_PIO0_10 register -PIO0_10 Possible solution Connect PIO0_2 and PIO0_3 to the debug connector for debugging. More resources in win...
Code Read Protection (CRP) is a mechanism that allows you to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in Flash location at 0x000002FC. If value 0...
Possible solution 1. Open Hardware |CPU Options |Reset. 2. Add a custom EVE script Connect To SoC Using TnDCM Reset to I nitialization before Programming | Connect . 3. Check the Same as Programming in Initialization before Debug Session section. 4. Edit the script parameters via the arrow...
Microcontrollers of the STMicroelectronics STM32H7 family have a special Flash Configuration Field where different settings for Flash programming can be adjusted. Possible solution 1. Open Hardware | device | Configure | FLAGS Configuration . 2. Configure according to your use case: Parall...
The Chip Erase script removes the security on the chip (if not permanently secured). The script is executed manually. In cases where the device is secured or possibly a malfunctioning application is loaded on it, the Chip Erase command allows to erase memories of the device and provides se...
Traveo II devices require a debug interface operating at a frequency higher than 1500 kHz. This permits the debugger to execute the necessary debug initialization procedures fast enough and within the device start-up time window constraint after the CPU reset line is released by the BlueBo...
The peripherals on Traveo II devices, such as timers, are not frozen by default when the device is halted in debugging. CYT4DN CYT4BF CYT4BB CYT3DL CYT3BB CYT2BL CYT2B9 CYT2B7 CYT2B6 Possible solution Custominitialization scripts are distributed with winIDEA to freeze the Traveo's peripher...
Password and Challenge/Response authentication are secure debug modes that prevent unauthorized access to the SoC by requiring correct credentials at the start of a debug session. Once authenticated, the SoC remains unsecured until a power-on-reset or similar reset occurs. For Password aut...
While using winIDEA you encounter an error related to debug password configuration, e.g. Debug access failed . Possible solutions Verify endianness It's possible that the endianness of the provided password is incorrect. For example, if you programmed the password into UTEST as 0x00, 0x01,...
Trace recording is incomplete because of the big gaps in time and trace message number, with ITM Synchronization lost messages in between.This typically happens due to the SWO clock instability, or too high of SWO data rate. Possible solution 1. Update to the latest winIDEA version . 2. Ad...
Additional configuration is required when using Attach/Detach procedure in conjunction with the workaround proposed to the M7 application core hung state erratum (ERR051149). Refer to the NXP errata documentation for a more detailed description and the proposed workaround. Solution Perform...
The LPC4357 is a dual-core with ARM Cortex-M4 and Cortex-M0 cores, which are accessed via the following Debug Protocols: Cortex-M4 on JTAG and SWD Cortex-M0 only on JTAG By default winIDEA tries to connect to all available cores. When selecting the SWD Debug Protocol, winIDEA should connec...
Debug session with Cypress Traveo II VIRGIN (life cycle) devices will be established partially - the core will not be stopped at the start of your application. Debugging VIRGIN devices is not supported from winIDEA 9.21.29. To inspect if you have a VIRGIN device refer to topic Reset and Fl...
Cypress S70FS01GS Flash non-volatile memory device implements JEDEC standard supporting Serial Flash Discoverable Parameters (SFDP). However, the S70FS01GS device is a dual die stack of two FS512S dies with consecutive memory addresses and prior to the first use initial formatting is requi...
Possible solutions LPC devices The most common cause is that the image programmed in the Flash prevents any further debug access or connections and fails to establish a debug session. The image usually contains code that: Sets the SoC clocks up incorrectly Enables a watchdog timer This put...
Possible solution 1. Select Debug |Prepare to Attach . 2. If using Hot Attach, follow the Hot Attach procedure to safely attach to the Target. 3. Select Hardware |Scripts |Unsecure (can also be Chip Erase or similar). This operation needs JTAG/SWD debug port to be accessible. Devices, wher...
Possible solutions: Check if the correct Device is selected Open Debug |Configure session | SoCs |Edit and check if the correct Device is selected. Configure New Workspace Follow the correct steps when Configuring a New Workspace .
Possible solution Verify the Reset methodselection in the Hardware |CPU Options |Reset. Explanation On Cortex devices internal reset logic can be implemented in various ways. The debug tool must be aware of the reset logic implementation to connect to the target microcontroller and gain co...
For Texas Instruments AWR18xx and AWR68xx devices, the ROM must be eclipsed with the RAM content after the bootloader. This process requires manual enabling of ROM eclipsing, followed by a soft reset. Possible solution 1. Select Hardware | Scripts | SoftResetCR4 . 2. Retry Download once th...
The flash bootloader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or user application code, or, in the case of the LPC13xx, it can obtain the boot image as an attached MSC device through USB. A LOW level during reset at pin PIO...
Per LPC435x specification, Cortex-M0 is not accessible through the SWD debug interface. It’s accessible only through the JTAG debug interface. It’s recommended to use the JTAG debug interface when debugging LPC435x, which allows debugging both Cortex-M4 and Cortex-M0 cores . If only the SW...
On Cortex-M devices from the LPC family a Boot Rom is present with: Code that is executed on reset A memory mapping register (MEMMAP, SYSMEMREMAP) After the debug connection is established: The target core is released from reset and stopped at the beginning of the boot code. The initial st...
Kinetis devices encompass a range of models, each offering different levels of Embedded Trace Macrocell (ETM) capabilities and parallel trace output pins. To determine the specific features available on your target device, please consult the corresponding reference manual. Affected familie...
In general, for a real-time observation of the variables these must be written in the data memory and not for example only held in the cache since cache memory is not visible to the debugger. If you want the "cached only" variables to be seen by the debugger, use the provided L1 Cache Writ...
Kinetis K2x The NXP Kinetis K2x series microcontrollers contain a 16-byte flash configuration field within the program flash memory. This field is essential as it stores default protection settings (loaded on reset) and security information, enabling the MCU to restrict access to the flash...
On LPC15xx devices you can configure I/O pin to use for a SWO trace with a custom initialization script. Environment will remap the selected pin to output SWO trace, disabling any function previously assigned by the application. Possible solution 1.Add the custom script LPC15xx_TraceInit.c...
These configuration steps arerequired to connect BlueBox to the Target andperform a CPU Reset, which establishes the initial Debug connection. Solution 1. Create a New Workspace via File | Workspace | New Workspace . 2. Open Hardware | CPU Options | SoC: a. Select JTAG or SWD under the Deb...
These topics describe how to start debugging the Arm Cortex-M7 and A53 / Arm Cortex-M33 or Cortex-R52 cores if no valid boot image is found on: Cold Start with NXP S32G/S32R Arm Cortex-M7 or A53 core Cold Start with NXP S32E2/Z2 Arm Cortex-M7 or A53 core
RCAR-S4 consists of Arm Cortex and G4MH cores. If you use an evaluation board you have to use different debug connectors and change some switches. Configure evaluation board The evaluation board has 2 debug connectors, for Cortex and G4MH cores. Make sure you use the correct debug adapter ...
The error means that the debugger failed to connect to the target CPU. This can be for different reasons. When troubleshooting the initial debug connection to the target CPU, it is recommended to use the CPU Reset instead of Download. Possible causes and solutions BlueBox is not properly c...
Flash on TMS570 devices features an ECC functionality. The ECC area can be programmed automatically with values corresponding to downloaded data or you can provide your own ECC download data. The option for automatic ECC generation is located in Hardware | TI TMS570 | Configure | FLAGS Con...
CC265xx devices support configuring the DIO pin on which the Serial Wire Output (SWO) trace is output. Possible solution 1. SWO output must be connected to the TDO pin of the Arm adapter. 2. Select cJTAG Debug Protocol in Hardware | CPU Options | SoC . Since the JTAG protocol uses TDO for ...
The JTAG chain is configurable within Zynq SoC. Cascaded JTAG works with an empty device. You must provide a soft core to connect external pins to Arm DAP if Independent JTAG mode is desired. Refer to Mode Pin Settings and JTAG and DAP Subsystem chapters in the Zynq reference manual for mo...
XMC devices implement a special functionality for stopping the CPU at the reset vector after reset when the debugger is connected. Possible solution 1. Go to Hardware | CPU Options | Reset | Reset pin. 2. Select the Regular Reset method. More resources in winIDEA Help Reset
The flash bootloader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or user application code. A LOW level after reset at pin P2.10 is considered an external hardware request to start the ISP command handler. Assuming that power s...
When using the winIDEA Memory window to view memory that should be inaccessible, you may notice a discrepancy in the memory display between the Virtual and IPmemory areas. Specifically, the Virtualmemory area displays "00" values instead of the expected "??," while the IP memory area corre...
SmartFusion2 devices have threshold detection for the number of writes performed on flash memory. When this threshold is reached flash programming API returns an error status. Possible solution 1. Open Hardware | device | Configure | FLAGS Configuration . 2. Select IgnoreWriteThresholdErro...
eFuses are OTP (One-Time Programmable) memory and can be used for several purposes.These how-to guides describe how to read or write eFuses using Python script on: NXP S32G/S32R NXP S32S Technical Note for NXP S32S includes confidential information and NDA with the silicon vendor is requir...
Error 304 means the BlueBox fails to connect and establish debug session with theCortex-M-basedtarget CPU. Possible solutions Use the Reset debug command When troubleshooting the initial debug connection to the target CPU, it's recommended to use the CPU Reset debug command instead of the ...
You can debug i.MX 8QuadMax M4 Processor cores using boot image where all application cores are booted and using boot image where only M4_0 core is booted. More information in winIDEA Help How-to guide Debugging i.MX 8QuadMax M4 Processor .
The program flash memory on S32K1xx devices contains a specific region that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the FTFC module. This topic describes how to allow programming in winIDEA in this region that ...